A scientific technology calculation is one of computer-assisted fields. A floating-point arithmetic is an important function in the scientific technology calculation. One of floating-point number representations in the computer is a representation for binary floating-point numbers according to the IEEE form (a representation for floating-point numbers based on the binary floating-point number representation form established by the IEEE, i.e., Institute of Electrical and Electronic Engineers). "NaN" exclusive of a numeric value is defined in the binary floating-point number based on the IEEE form. NaN is treated differently from the numeric value, and therefore a floating-point number processor requires a detection of NaN.
A floating-point number representation in the IEEE form is a representation based on a bit structure generally having a sign bit, exponent bits and fraction bits. This floating-point number representation is classified into the following forms.
(1) Single Precision Floating-Point Number PA0 (2) Double Precision Floating-Point Number PA0 (3) Extended Double Precision Floating-Point Number
A single precision floating-point number in the IEEE form has, as illustrated in FIG. 38, a 1-bit sign part s indicating positive/negative signs, an 8-bit exponent part e indicating a bias exponent in an exponent representation, a 23-bit fraction part f indicating a fraction in the exponent representation and an undefined area. The single precision floating-point number is substantially expressed in 32 bits, i.e., 4 bytes.
In this case, the bit structure goes as follows:
______________________________________ Sign s Positive number when being `0` but negative number when being `1` Bias exponent e Minimum exponent value 0 Bias exponent 1-254 Maximum exponent value 255 Bias value 127 Decimal point position Most significant integer L e = 0 L = 0 0 &lt; e &lt; 255 L = 1 e = 255 L = 0 Fraction f ______________________________________
A double precision number in the IEEE form has, as shown in FIG. 39, a 1-bit sign part s, a 11-bit exponent part e and a 52-bit fraction part f. The double precision floating-point number is expressed in 64 bits, i.e., 8 bytes.
In this case, a bit structure goes as follows:
______________________________________ Sign s Positive number when being `0` but negative number when being `1` Bias exponent e Minimum exponent value 0 Bias exponent 1-2046 Maximum exponent value 2047 Bias value 1023 Decimal point position Most significant integer L e = 0 L = 0 0 &lt; e &lt; 2047 L = 1 e = 2047 L = 0 Fraction f ______________________________________
An extended double precision floating-point number in the IEEE form has, as illustrated in FIG. 40, a 1-bit sign part s, a 15-bit exponent part e, a 64-bit fraction part f and an undefined area (48 bits).
In this case, a bit structure goes as follows:
______________________________________ Sign s Positive number when being `0` but negative number when being `1` Bias exponent e Minimum exponent 0 value Bias exponent 1-32766 Maximum exponent 32767 value Bias value 16383 Decimal point position Most significant integer L e = 0 L = 0, 1 0 &lt; e &lt; 32767 L = 0, 1 e = 32767 L = unsigni- ficant Fraction f ______________________________________
Supposing that the numeric values are normalized (the most significant bit of the fraction part takes a form of "1"), a value of the floating-point number is expressed in the following representation formula. EQU (-1).sup.s .times.2.sup.e .times.(1.f)
By the way, "NAN" is defined in the IEEE form to distinguish normal values from special values as in the case of producing a result when dividing the numeric value by 0 or an overflow. The definition of NaN in the IEEE form is that the exponent part e takes the maximum exponent value, and the fraction part f is not "ALL `0`". In other words, if the exponent part e is "ALL `1`", and if even one bit of `1` is contained in the value of the fraction part f, the data is defined as NaN.
This kind of NaN detection in the floating-point number has hitherto involved the use of methods which follow:
(a) A dedicated NaN detector is provided for every precision (a number of significant digits) in order to perform the NaN detection. When using the data, NaN is detected by a NaN detector corresponding to a precision of the data among a plurality of NaN detectors.
(b) A data representation form to deal with the data in the processor is transformed into a 1-bit extended data form. The NaN detection is effected beforehand when inputting the data to the processor. A result thereof is set as a NaN flag and stored in the 1-bit extended part. A NaN discrimination is conducted based on this NaN flag.
It is, however, required in the method (a) that the NaN detector be prepared for every precision. Further, according to the method (b), when saving/restoring the data in the processor, generally, a memory for saving does not correspond to the data representation form with the extension of the NaN flag bit. No area for storing the NaN flag does not exist on the memory for saving. This conduces to a problem in which the NaN flag is deleted when saved/restored.